1. Field of the Invention
The present invention relates to an FET provided with a back gate region structure, particularly to a power FET for controlling a high voltage and a large current.
2. Description of Related Art
A power FET is used to control a high voltage and a large current and, for example, used for the output stage of a motor-control IC. This type of the transistor is normally provided with a back gate region for keeping a threshold voltage constant.
A back gate region may be provided for a small-current MOSFET for logic but its structure is extremely different from that of a power MOSFET.
FIGS. 1 and 2 show a back gate region provided for a small-current MOSFET for logic. FIG. 1 shows a top view of the arrangement of regions of a drain, a gate, a source, and a back gate and FIG. 2 is a sectional view. In FIGS. 1 and 2, hatching for sectional views is omitted for simplification and a reference number is provided for only a drain region 1, a gate region 2, a source region 3, a back-gate region 4, a channel-forming region 6, a body well 7, a source electrode 12, and a drain electrode 13.
In the case of this example, potentials of the body well 7 and source region 3 including the channel-forming region 6 are equalized each other by the back-gate region 4. The back-gate region 4 and the body well 7 are contacted each other at a portion separate from the source region 3. When using the above structure, the distance between the back-gate region 4 and the channel-forming region 6 is increased and a parasitic resistance 8 is generated at the portion between the regions 4 and 6. However, because a large current does not normally flow through a back-gate region in the case of a small-current MOSFET, rise of the back-gate-region potential due to the parasitic resistance 8 does not frequently occur.
In the case of a power MOSFET, however, because a large current flows through a back-gate region, the parasitic resistance 8 occurs when using the above structure. That is, a potential difference occurs between the back-gate region 4 and the channel-forming region 6 due to the parasitic resistance 8 and thereby, a parasitic bipolar transistor operates which uses the channel-forming region 6 as a base and the drain region 1 and the source region 3 respectively adjacent to the region 6 as a collector and an emitter. Thereby, a large current flows through a body diode parasitically constituted of the back-gate region 4 and the source region 3. For example, when using a coil as a load, a voltage equal to or higher than the drain withstand voltage of a power MOSFET (that is, the withstand voltage of the body diode) due to the back electromotive force generated in the coil or higher is applied to the power MOSFET and thereby, the power MOSFET may be broken down. Moreover, when constituting an H bridge circuit, a forward-directional large current flows through a body diode and thereby, a latch-up phenomenon may occur.
To prevent the parasitic bipolar transistor from operating, it is effective to equalize the potential of the back-gate region serving as a base with that of the source region serving as an emitter. FIGS. 3 to 5 show a first prior art for equalizing the potential of a back-gate region with that of a source region. FIG. 3 is a top view of the arrangement of a gate electrode, a source region, and a back-gate region, and FIG. 4 is a sectional view of the arrangement taken along the line 4--4 of FIG. 3 and FIG. 5 is a sectional view of the arrangement taken along the line 5--5 of FIG. 3. This structure is disclosed in U.S. Pat. No. 5,656,517, in which a back-gate region 4 is formed in a source region 3. The potential of the back-gate region 4 is equalized with those of a body well 7 (region serving as the base of a parasitic bipolar transistor) and the source region 3 including a channel-forming region 6 by a source wiring and a source electrode 12.
FIGS. 6 and 7 show a second prior art provided with a back-gate region. FIG. 6 is an illustration showing the planar arrangement of a gate electrode, a source region, and a back-gate region and FIG. 7 is a sectional view of the arrangement taken along the line 7--7 of FIG. 6. This structure is disclosed in the official gazette of Japanese Patent Laid-Open No. 4-225569. This example has a structure in which the back-gate region 4 is extended up to the channel-forming region 6 immediately below the gate electrode. The back-gate region 4 is connected to the source electrode 12 and its potential is equalized with that of the body well 7 (region serving as the base of a parasitic bipolar transistor) including the channel-forming region 6.
Conventional examples related to a horizontal FET are described above. FIGS. 8 to 10 show a third prior art related to a vertical FET. FIG. 8 is an illustration showing the planar arrangement of a gate electrode, a source region, and a back-gate region, FIG. 9 is a sectional view of the arrangement taken along the line 9--9 of FIG. 8, and FIG. 9 is a sectional view of the arrangement taken along the line 10--10 of FIG. 8. The back-gate region 4 is formed in the source region 3. The potential of the back-gate region 4 is equalized with those of a body well 7 (region serving as the base of a parasitic bipolar transistor) and the source region 3 including a channel-forming region 6 by a source wiring.
The above prior arts respectively have a purpose for preventing a parasitic bipolar transistor from operating by equalizing the potential of a channel-forming region with that of a source region. However, each of the prior arts has the following problems.
In the case of the first prior art shown in FIGS. 3 to 5, because the back-gate region 4 is embedded in the source region 3, a parasitic bipolar transistor operates in which the resistance of the diffusion layer at the portion immediately below the source region serves as a parasitic base resistance. The parasitic bipolar transistor originally easily causes thermal runaway. Particularly, the breakdown tolerance dose when breaking down the junction by applying a high voltage between a collector and an emitter is too low, this is a problem. Moreover, in the case of the third prior art shown in FIGS. 8 to 10, because the back-gate region 4 is embedded in the source region 3, the resistance of the diffusion layer at the portion immediately below the source region serves as a parasitic base resistance and thereby, the same problem occurs.
However, the second prior art shown in FIGS. 6 and 7 makes it possible to reduce the above parasitic base resistance and prevent a parasitic bipolar transistor from operating by extending a part of the back-gate region 4 up to the region immediately below the gate electrode 2. However, the region immediately below the gate electrode 2 is the channel-forming region 6 of the FET and therefore, the back-gate region 4 breaks into the path of carriers discharged from the source region 3. Therefore, a problem occurs that a channel resistance increases. Because the back-gate region 4 is further horizontally expanded by undergoing heat treatment in the subsequent annealing step, the problem of increase of the channel resistance becomes more serious.